The answers are a mix of pseudo-code and simplified block diagram. They are intended to reflect the conceptual solution. Other implementation options are possible (this is actually what many of interviewers would expect). As opposite to SW interview in HW interview nobody would expect any single stone-graven scripture because you are not given all the system knowledge. When you write the real RTL you know the system, requirements, tons of all the accompanying data which influences the solution. At interview you just need to express your way of thinking and your awareness of possible limitations and constraints. Actual Verilog knowledge is rarely been asked.
The sample answer for the first question is depicted below. It well expresses the spirit of things.
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Answer: To find the synch pattern two methods may be applied: FSM and shift register. The FSM will have 7-8 states and thus will need 3 bits state storage. Shift register will be 7-8 bits deep. While FSM solution has less bits, we will choose shift register solution because first we will anyway want to accumulate 8 bits of data to store them at once, second the difference of 5 bits storage is not a big deal. From the second hand the shift register solution is somewhat more straightforward. We will want to store enough data to be able to output as many synchronized data as we can, meaning data which was pre-collected even before the synch is established but which can be proved to be in synch. When the synch is declared, two frames of previously collected data are already in synch and worth not to be lost. And the logic is as follows:
//first_synch – indication of first pattern recognition after reset
assign first_synch = ({in,sr[6:0]} == ‘he8) && (cnt3 == 2’d0);
//synch – indication of any following pattern recognition which is in sync
assign synch = ({in,sr[6:0]} == ‘he8) && (cnt3 > 2’d0) && (cnt128 == ‘d127);
//resynch - indication of any following pattern recognition which is not in sync
assign resynch = ({in,sr[6:0]} == ‘he8) && (cnt3 > 2’d0) && (cnt128 != ‘d127);
//cnt3 – counter for 3 frames
always @ (clk)
if (!rst_n)
cnt3 <= 2’d0;
else if (vld_in && first_sync)
cnt3 <= 2’d1;
else if (vld_in && resynch)
cnt3 <= 2’d1;
else if (vld_in && synch && (cnt3 != 2’d3)) //stuck at 3
cnt3 <= cnt3 + ‘d1;
//cnt128 – counter for 128b in frame
always @ (clk)
if (!rst_n)
cnt128 <= 8’d0;
else if (vld_in && first_synch)
cnt128 <= 8’d0;
else if (vld_in && resynch)
cnt128 <= 8’d0;
else if (vld_in && (cnt3 > 2’d0))
cnt128 <= cnt128 + ‘d1;
//push – push to FIFO
assign push = vld_in && (first_synch | (cnt128[2:0] == ‘h7));
//pop - pop from the FIFO
assign pop = vld_out;
//in_synch – the data is in sync
always @ (clk)
if (!rst_n)
in_synch <= 1’b0;
else if (synch && (cnt3 == 2’d2))
in_synch <= 1’b1;
//vld_out – valid at the output from the block
assign vld_out = ~fifo_empty && (synch | in_synch);
